This paper compares the bandwidth available to processors resident on the payload boards using the CEN16 switched architecture for Serial RapidIO and 10 Gigabit Ethernet (10GbE). The analysis compares two different "benchmark" data flow models, the classic all-to-all case typical of a corner turn operation, and a pipeline case.

The analysis will show that the SRIO systems have more than three times greater bandwidth than 10GbE, and that half of that improvement is due to the more flexible routing afforded by actual hardware implementations that can be achieved with SRIO silicon.