Serial RapidIO-to-PCIe Intelligent Bridge Core

Mercury Systems

Flag/report this product
At this monthís Bus&Boards insidersí conference in Long Beach, California, the fabric interconnect RapidIO was everywhere you looked. It seems that Serial RapidIO is becoming the interconnect of choice for high-performance VME systems, supplemented by PCI Express and GbE. With all three interconnects so prevalent, the need for bridging between them is becoming acute. While PCIe-to-Ethernet bridges are common consumer items straight from desktop PC and server products, Mercury Computer is making it easy to bridge between PCIe and Serial RapidIO with their Serial RapidIO-to-PCIe Intelligent Bridge Core. Available as Verilog HDL in either Synopsis or Synplicity synthesis environments, the core can be implemented in FPGAs, ASICs, ASSPs, or SoC devices. We suspect that for VME systems, the FPGA will prevail. The core connects a Serial RapidIO port (RapidIO 1.2) operating at up to 3.125 GHz to an x8 PCI Express port (PCI Express 1.1) operating at 2.5 GHz through a nontransparent bridge. The core includes myriad high-level functions pertinent to RapidIOís value proposition of solving high-speed problems in hardware (while reducing software and processor overhead). Multiple DMA engines, Serial RapidIO mailboxes and interrupts, address mapping, and sophisticated queuing within the intelligent bridge assure high utilization while maintaining maximum port bandwidth. The Verilog HDL targets FPGAs from Altera, Lattice, and Xilinx, and 0.09 micron (or smaller) line width geometries for custom silicon implementations.
Serial RapidIO-to-PCIe Intelligent Bridge Core

FEATURES

  • A Serial -to-PCIe Intelligent Bridge Core
  • Available as HDL in either Synopsis or Synplicity synthesis environments
  • Core can be implemented in , ASICs, ASSPs, or SoC devices
  • Core connects a Serial RapidIO port (RapidIO 1.2) operating at up to 3.125 GHz to an x8 PCI Express port (PCI Express 1.1) operating at 2.5 GHz through a nontransparent bridge
  • Multiple DMA engines, Serial RapidIO mailboxes and interrupts, address mapping, and sophisticated queuing within the intelligent bridge assure high utilization while maintaining maximum port bandwidth
  • Verilog HDL targets FPGAs from Altera, Lattice, and Xilinx, and 0.09 micron (or smaller) line width geometries for custom silicon implementations

See also:

Go Back

Topics covered in this article

Flag/report this product