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  • 32-bit RISC soft core optimized for implementation in Xilinx FPGAs
  • Thirty-two 32-bit general purpose registers
  • 32-bit instruction word with three operands and two addressing modes
  • 32-bit address bus
  • Single issue pipeline
  • Hardware acceleration using Fast Simplex Link (FSL)
  • IEEE-754 compatible Floating Point Unit (FPU) option
  • Configurable features such as barrel shifter, divider, multiplier, instruction and data caches, FPU, FSL interfaces, hardware debug logic, and hardware exceptions
  • Included in the Embedded Development Kit (EDK)

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