Riviera-IPT

ALDEC, Inc

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A high-speed co-verification and debug environment for complex embedded software/hardware co-development utilizing ARM processors

FEATURES

  • ?Based on Aldec+IBk-s VHDL and Verilog mixed-language simulation technology, Design Verification Manager, and a hardware accelerator with capacity up to 12 million gates
  • Riviera-IPT+IBk-s hardware accelerator allows designs to run at MHz speeds
  • Supports IEEE VHDL 1076-87/93, VITAL 2000, and Verilog 1364-2001

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