Optical interconnects to bolster digital microelectronics
WASHINGTON. Researchers from Intel and Ayar Labs working on DARPA’s Photonics in the Package for Extreme Scalability (PIPES) program have replaced the traditional electrical input/output (I/O) of a state-of-the-art field programmable gate array (FPGA) with efficient optical signaling interfaces.
The demonstration leverages an optical interface developed by Ayar Labs called TeraPHY, an optical I/O chiplet that replaces electrical serializer/deserializer (SERDES) chiplets. These SERDES chiplets traditionally compensate for limited I/O when there is a need for fast data movement, enabling high-speed communications and other capabilities.
Using Intel’s advanced packaging and interconnect technology, the team integrated TeraPHY and the Intel FPGA core within a single package, creating a multi-chip module (MCM) with in-package optics. The integrated solution is designed to improve interconnect reach, efficiency, and latency – enabling high-speed data links with single mode optical fibers coming directly from the FPGA.
Built in GlobalFoundries’ advanced photonics process, the co-packaged TeraPHY chiplet used for this demonstration is capable of 2 Terabits per second (Tbps) of I/O bandwidth at a small fraction of power compared to electrical I/O, according to the companies.