Forty years since its release, MIL-STD-1553 is evolving from traditional Integrated Circuits (ICs) to Intellectual Property (IP) cores integrated with Field Programmable Gate Arrays (FPGAs). The advantages of IP core implementation include cost reduction, the ability to upgrade and adapt a design over time, a smaller size footprint, and improved sourcing. Designers choosing IP cores must consider validation testing, code size, FPGA support, and compatibility with legacy software.
Mil Tech Trends
The transition to DO-178C continues to improve guidelines for avionics certification – however, big questions still surround the regulation of Unmanned Aerial Vehicles (UAVs) in national airspace and how industry and government will go about ensuring that these drones are safe to fly daily in the same skies as passenger aircraft.
Avionics system architects making design decisions today are often frustrated by an expensive problem - having to perform a substantial redesign because an existing system lacked the flexibility required to support an update. Such inflexible barriers in the design process may be overcome by using new, highly-integrated multi-core processors that can provide long-term system flexibility. Multi-core processors are now being utilized to not only address the dwindling availability of new single-core processors, but also to take advantage of increased throughput while maintaining equivalent power consumption.
Modern radar and electronic warfare designs rely heavily on embedded computing systems that leverage high-speed commercial processors and FPGAs to find every target or signal and enable the warfighter to respond in real time. Meanwhile, signal processing system designers are cutting costs by using parallel compute platforms such as OpenCL that work across multiple chip platforms.
Due to shrinking Department of Defense (DoD) budgets and ever-decreasing platform size, the need to use common apertures and sensor chain elements for Electronic Warfare (EW) and radar systems is becoming a necessity. System developers must use common elements from Radio Frequency (RF) to processing to build such systems. The linchpin of these types of sensor-based systems is the I/O interface between the RF and processing elements. FPGAs have traditionally been used as this I/O interface, but now they are serving as an integral part of the processing subsystem on common EW radar systems.
Military applications such as radar, Software Defined Radio (SDR), smart munitions and target detection systems, Electronic Warfare (EW), aircraft imaging, and many more benefit from Digital Signal Processors (DSPs). DSPs accelerate performance using deterministic processing and have capabilities that include real-time signal processing, extremely high throughput, and reprogrammability. However, signal processing demands for radar, EW, and other programs continue to increase so DSP system users continue to search for innovation that will boost performance. That need is being answered by use of a combination of Quad Data Rate (QDR) Static Random Access Memory (SRAM) that - at a minimum - doubles the performance of more traditional Synchronous Dynamic Random Access Memory (SDRAM).
Effective fusion of multiple sensors such as radar video and cameras is the key to presenting a situational display in military security applications that successfully informs the operator and supports critical decision-making. However, while track display with track fusion offers the benefits of simplifying the display presentation based on an assessment of threat, this approach is only as effective as the rules used to process, filter, and select the information. Complementing the processed display with the ability to show primary sensor data allows for simplified presentation of complex information where there is confidence in the data interpretation, while still permitting the operator to observe raw sensor data for manual interpretation, verification, or simply reassurance.
Improved power-to-performance ratios with multicore processors in VPX systems are boosting viability and reducing reliance on the high costs of FPGA development. Since they fundamentally change the way signal processing is implemented, parallel-rate microprocessors do away with hand-coding threads and math algorithms and more efficiently bring together powerful computing platforms that can take full advantage of state-of-the-art processor features. (Lead image: U.S. Army Spc. Nathan Williams from the 263rd Army Air Missile Defense Command deploys a Sentinel radar system. Radar systems like Sentinel depend on high-performance signal processing systems. DoD photo by Staff Sgt. Jacob N. Bailey, U.S. Air Force.)
High density power electronics with high efficiencies – typically more than 90 percent – are becoming the defacto requirement for high-end mission critical military platforms such as radar, fighter jets, UAVs, and weapon systems where size, weight, and power are limited. Meanwhile, Gallium Nitride based RF components are beginning to populate military RF applications.
Wireless power, a new technology already poised to change the way we recharge everything from smart phones to electric vehicles, has the unique potential to transform war fighting of the future and alleviate the battlefield battery burden for both soldiers and manned and unmanned vehicles on land, in the air, and undersea. The U.S. military goals of digitizing dismounted soldiers, sensing their environment, and sharing information could require as much as twice the power as is required by warfighters today; the already burdensome tasks of carrying, operating, and maintaining multiple batteries, cords, and connectors will only be exacerbated unless dramatic changes in power management are implemented using highly resonant Wireless Power Transfer (WPT) systems.