Using VITA 75 and standards-based modular design to address SWaP-C challenges

4As the world's armed forces look to deploy computing capability and unmanned vehicles ever closer to the battlefield edge, size, weight, and power (SWaP) are at a premium. The use of modular building blocks such as COM Express (PICMG COM.0) and/or XMC (VITA 42) – and, for packaging, the rugged small form factor (VITA 75) – represent an excellent means to address the requirements of minimizing size, weight, power, and cost (SWaP-C).

COM Express is an industry standard for computer-on-module that has been around for more than five years and has been widely adopted within the embedded computing industry. A COM Express module provides all the components necessary for a bootable host computer, with a standard set of I/O including Ethernet, PCIe, SATA, USB, and video that is then connected (via predefined connectors and I/O scheme) to a carrier. The carrier is required to break out the signals needed for a complete subsystem. Several sizes have been defined for the modules, enabling good scalability to a large set of applications. The COM Express basic module is defined to be 95 mm x 125 mm.

Although it’s well suited to embedded applications, COM Express is not inherently suited to very extreme applications, such as the shock and vibration often found in airborne and ground vehicle applications. Historically, the technology has largely been deployed in benign industrial environments.

This shortcoming on the basic module can, however, be overcome by adding mounting holes. The base specification defines five mounting holes around the edge of the module for mounting, a configuration that leaves the middle of the board (especially in the area of the connector on a Type 6 module) somewhat subject to movement when stressed by vibration. Adding three holes (as seen in Figure 1) to relieve that movement provides for a very rugged module that can be readily used in harsh environments.

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Figure 1: Providing additional mounting holes significantly increases the ability of COM Express technology to be deployed in harsh environments.
(Click graphic to zoom by 1.9x)

In deployed environments where SWaP is constrained, the additional issue of cooling requires innovative techniques to ensure excellent thermal contact to the CPU die of the module and eliminate the issues posed by height and tolerance mismatches of the CPU die. These techniques are particularly important when working with today’s higher-power quad-core processors such as the 3rd and 4th generation i7 CPUs from Intel or multicore Power Architecture CPUs available from Freescale.

COM Express can also provide a good technology migration path, as consideration has been given to the latest high-speed protocols such as PCIe Gen 3. While some special design considerations – such as PCIe re-drivers – may be required, the standard can handle the task of supporting the high-speed protocols that the latest generation processors provide.

Moreover, the modular approach provides excellent risk mitigation in terms of technology obsolescence and the opportunity for cost-effective technology insertion. As technology evolves, modules can be replaced and/or updated as needed, allowing support for long life cycle programs. While module replacement would not be done in the field, the actual update could be performed with minimal effect and could well have no impact on the cooling or power considerations of the platform.

XMC mezzanine standard

XMC is a mezzanine standard that supports switched high-speed interconnect protocols (such as PCIe Gen 1/2/3). Use of XMC as an expansion mezzanine within a subsystem is an excellent choice, as it provides the ability to bring in application-specific capability such as communications (1553 and/or ARINC, for example), graphics, storage, and many others. Moreover, it defines a robust connector system for the fabric and I/O, allowing support for a wide range of applications.

A somewhat recent update to the XMC standard (XMC 2.0) is the addition of an alternative connector (VITA 61) that has been electrically characterized to support 7.5 Gbps, allowing support for PCIe Gen 2 (with good margin) and the possibility of supporting Gen 3 (simulation recommended). As XMC is defined to support both air- and conduction-cooled applications, it is readily applicable to harsh environments.

VITA 75 rugged small form factor

VITA 75 is the response to the accelerating customer demand for increasingly small, lightweight, embedded computing subsystems. It defines the envelope within which the subsystem must fit, the external power and signal interfaces, the mechanical mounting interfaces, and any cooling interfaces. VITA 75 also addresses what’s inside the box.

Currently, VITA 75 is a rugged small form factor (SFF) trial use standard that has been available for about two years. The intent is for the trial to extend to about 36 months; at that point, input will be collected and revisions made as needed and it will likely move forward for submission to ANSI.

Several elements of VITA 75 make it particularly compelling in applications where SWaP-C needs to be minimized. First, it allows for a range of front-panel profiles, so that connector and I/O needs can be addressed as needed. Next, it defines a wide range of envelopes, with the smallest occupying a volume of less than 0.05 cubic feet. One of the most compelling elements of VITA 75 is that it defines various types of modules (printed wire assemblies) supporting both bladed – with a module plugged into a backplane – and stacked, featuring modules plugged into each other with no backplane required. As the specification evolves, other module types may be envisioned and defined as needed.

Three types of cooling are currently defined to enable a range of applications: free convection, forced air, and conduct to cold plate. Generally, most applications of the standard will involve either forced air or conduct to cold plate cooling.

Combining COM Express and XMC within VITA 75 for a complete SFF subsystem

Embedded system design involves, inevitably, a series of tradeoffs in which the designer allocates appropriate priority to key characteristics – which include, at the top level, a trade-off between raw computing performance on the one hand, and SWaP on the other. The goal is typically to maximize available throughput while minimizing SWaP.

Representative of what’s possible today is GE’s MAGIC1 (see Figure 2). Based on the VITA OpenVPX standard in its 3U form, this rugged SFF system delivers a lower SWaP profile with its size of less than 0.1 cubic feet, weight of less than 12 pounds, and power consumption of less than 120 W. By combining a single-board computer (SBC) and a graphics processing unit (GPU), it allows a relatively small, lightweight subsystem to deliver >900 GFLOPS of peak performance.

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Figure 2: GE’s MAGIC1 rugged display computer can deliver over 900 GFLOPS of performance from a small, lightweight subsystem.
(Click graphic to zoom by 1.9x)

While such a system has many applications, it might not be suitable for applications where such significant processing power is unnecessary but minimal SWaP is a high priority.

Using the modular building blocks discussed above, together with VITA 75, it’s possible to envisage a SFF subsystem (see Figure 3) with the characteristics required of a system with substantially superior SWaP to the 3U VPX system described previously. With the use of a quad-core Intel architecture COM Express basic module, along with other I/O as needed (1553 via an XMC, for example), a subsystem can be built that provides about 75 GFLOPS of peak compute performance. In this configuration, however, the size is much smaller at about 0.05 cubic feet, the weight is less than five pounds, and power consumption is less than 50 W. Of course, performance can be scaled back if very low power is a prerequisite (to maximize mission length, for example) to less than 25 W if needed.

One potentially significant advantage of taking this type of building-block approach is that higher-cost connectors and backplane systems can be avoided by stacking the building blocks (a COM Express module connected to a common carrier with the additional ability to host an XMC mezzanine for expansion). Such a stacked approach can also avoid some of the signal-integrity challenges that a traditional daughtercard/backplane approach may have. Special consideration is still required in the design, as connector-insertion loss, printed circuit board dielectric, and signal trace lengths must all be carefully managed to support high-speed protocols such as PCIe Gen 3.

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Figure 3: VITA 75/COM Express could be combined to deliver excellent compute performance from a subsystem with minimal size and weight requirements.
(Click graphic to zoom by 1.9x)

Standards-based modular approach

A modular approach, along with the correct subsystem standard such as COM Express, can enable excellent SWaP-C conditions. In the harsh environment of the battlefield, the combination of rugged COM Express, together with VITA 75, enables the development and deployment of subsystems that can be scaled across a range of envelopes and use a wide range of cooling and mounting techniques. Additionally, with the correct use of standards-based modular building blocks, stricter cost targets can be met, enabling a variety of applications such as small unmanned vehicles, large airframes, and even larger ground vehicle applications. The combination of COM Express and VITA 75 holds great promise for the challenges inherent in bringing increasingly powerful computing closer to the battlefield edge.

David Pepper is Product Manager/Technologist, Military/Aerospace Products for GE Intelligent Platforms. Over the past 16 years, he has primarily focused on standard form factors (CompactPCI, VME, and VPX) using ARM, Freescale, Intel, and NVIDIA technologies. David’s current efforts are towards achieving the highest compute densities possible in these form factors while continuing to recognize the need to address SWaP-C concerns. Prior to GE, David spent 19 years at NASA’s Marshall Space Flight Center. He has a BS from Athens State University and an MS from Southeastern Institute of Technology.

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