SWaP sweeps and edge processors adapt
Size, weight, and power (SWaP) considerations have always been important for embedded electronics, but as platforms shrink, SWaP constraints are becoming ever more critical. Larger platforms will, of course, continue to use “big” processors that are optimized for performance. However, the proliferation of intelligence at the tactical edge is driving military demand for rugged off-the-shelf chips, modules, and boards that provide just enough performance for their applications. These parts must burn minimal power and produce minimum heat but at the same time offer maximum design flexibility, upgradability, and support.
Autonomous air, ground, and sea platforms are being miniaturized to previously unheard-of levels. Moreover, the expanding, TCP/IP-powered, connected battlefield – analogous to the Industrial Internet in civilian life – means that more and more small machines at the edge are getting smart. The number of intelligent sensors, handheld devices, and wearable technologies, for example, will gradually increase, as they prove themselves force multipliers. As these machines run on batteries, they are extremely power-constrained. The higher the power consumption, the shorter the mission life.
These developments are increasing the demand for processing adaptations. Instead of aiming for the very highest data throughput, regardless of power and thermal costs, designers of these smaller systems are willing to trade MIPs (millions of instructions per second) for watts – in other words, pure performance for power efficiency. Power requirements, heat dissipation, and size will trump sheer speed in these applications. Performance per watt will mean more than MIPS per dollar.
Follow the phones
System and subsystem designers at this leading edge of the military’s evolution now are treading paths already blazed by cellphones and tablets. Today’s Apple and Android offerings combine voice, data, and video communications, games, calendar, alarm clock, and a myriad of other functions, yet require minimal silicon and dissipate negligible heat.
How do they pull this off? Like cellphone designers, military system developers are adopting low-power, low-heat architectures such as ARM. Not to be outdone, traditional chip developers also are adding functionally integrated, lower-power system-on-chip (SoC) architectures to their product lines.
This shift means moving from traditional central processing units (CPUs) to ultra-low-power chips. Low-power SoCs consolidate as many functions as possible into a single, highly integrated chipset, lowering the system’s overall size and thermal penalty. Their host platforms simply lack the space, size, and power budgets to dedicate a whole die to the CPU and so distribute memory controller, graphics processor, and other support to ancillary silicon.
This well-understood approach enables a high degree of flexibility and customization, as multiple manufacturers create implementations of standard architectures, using off-the-shelf chipset components. Due to commoditization at the subchip level, each processor can be tailored to the particular power and performance demands of the application.1
Military designers also are using XMC, an evolution of the PCI Express-based PMC (PCI mezzanine card) module, which provides a high degree of flexibility in a small form factor. Used with a low-power chip architecture and a minimum of other onboard resources, an XMC module can burn less than 10 W. These modules are themselves pluggable, allowing a range of CPU core and memory options to suit the customer’s roadmap.
An example of these new low-power modules is the GE Intelligent Platforms rugged XMCM01 XMC module, featuring the ARM-based ARMADA XP processor (see Figure 1).
Ironically, military imperatives, which initially drove the invention of transistors and integrated circuits, have circled around, in part, to enable processing that better suits the tradeoffs at the edge of the battlefield.
Similar developments in the commercial world have driven even more explosive growth of processing power at the edges of the Internet. Pundits predict that this burgeoning of intelligence at the peripheries will localize much processing, as bandwidth to the “cloud” of powerful servers at the center comes under pressure. How this movement will work itself out in the military and civil spheres remains to be seen, but the trend presents the command structure, at a minimum, with opportunities to speed some critical battlefield transactions by increasing processing efficiencies.
1 Robert Swope Fleming in “The End of the Intel Age,” his 2011 master’s thesis at MIT, p.11, explains this dynamic and the evolution of processing architectures.