Latest 40 Gbps SBCs drive new class of HPEC-Lite systems for ISR applications

The embedded defense and aerospace industry has recently seen the emergence of new embedded system elements that support 40 Gbps fabrics. These higher bandwidth hardware solutions include Single Board Computers (SBCs), DSP engines, GPGPUs, FPGA engines, network switches, and Gen3 OpenVPX backplanes. With their support for 40 Gigabit Ethernet (GbE) and QDR Infiniband (for board-to-board communication) and Gen3 PCI Express (for on-board data flows), these system elements enable the integration of large-scale rugged embedded subsystems that approach supercomputer processing levels. These high-end processing systems can now address challenging Intelligence, Surveillance, and Reconnaissance (ISR) applications in low- to mid-range systems with three to five boards in a small, compact chassis.

System designers can now use the latest generation of SBCs that feature dual channels of 40 Gbps bandwidth and support for 3rd Gen PCIe-enabled XMC mezzanine module sites to define a new class of entry-level “HPEC-Lite” systems. With their higher 40 Gbps bandwidth, the latest SBCs can now serve as dual-use platforms in small low- to medium-level High Performance Embedded Computing (HPEC) systems, providing both their traditional system management functionality and the high-speed data ingress functionality that previously required the use of a dedicated, but lower speed, XMC I/O carrier board in an ISR HPEC system.

Small HPEC systems such as the Curtiss-Wright 6U VPX6-1958 board bring in analog front-end data to the board via its high-speed I/O XMC mezzanine cards at PCI Express (PCIe) rates (see Figure 1). The raw captured data is then sent directly from the SBC at 40 Gbps rates to one or more DSP engines for ISR application processing. This “HPEC-Lite” approach eliminates the need for a slower, PCIe-based XMC carrier card and the dedicated board slot it would require. Instead, the SBC functions as a high-speed intelligent router that can run a TCP/IP stack to support a redundant 40 GbE data pipe to the system’s DSP engines. Via its dual/quad 40 Gbps pipes, Core i7 CPU, and high-speed XMC sites, the SBC becomes a high-end sensor I/O distribution subsystem.

21
Figure 1: Curtiss-Wright’s VPX6-1958 board, which uses the latest Intel 4th Generation Core i7 processor and dual XMC sites, enable HPEC-Lite systems for SWaP constrained ISR applications.
(Click graphic to zoom by 1.9x)

The SBC’s Intel 4th Generation Core Haswell processor, with its built-in GPU, can deliver unprecedented levels of performance – 300 GFLOPS from either the CPU or GPU, which combined brings more than 600 GFLOPS of performance from a single Intel processor. In an HPEC-Lite system like the one mentioned above – with a lone VPX6-1958 SBC and two DSP engines, the result is >2 TFLOPS of processing performance. This performance is expected to increase, as future Intel processors are anticipated to enable 4 TFLOPS in a similar 3-board small HPEC system.

Many ISR applications will continue to require larger board sets. However, the compact HPEC-Lite approach will enable many types of ISR applications with low Size, Weight, Power, and Cost (SWaP-C) requirements, to be solved with a small deployed chassis. For example, a radar-processing system can be built using the smaller system to bring in raw data at the front-end via Serial FPDP (sFPDP) via the SBC’s XMC cards, and then transfer that raw radar data with minimal latency to one of the system’s two DSPs for post processing.

Another potential application is visualization data processing, particularly when pattern matching is required in unmanned aerial vehicles, ground combat vehicles, and airborne sensor pods. In this type of application the SBC’s XMCs would use the XF05 camera link digital video-transmission standard to bring the raw video data to the small HPEC system, which would then route the data to the system’s DSP engines for post processing.

In this dual-use approach, the SBC is still able to provide the traditional “traffic cop” system management functionality, but now also acts as the ingress system for the front-end data, sending raw data via PCIe to dedicated GPGPUs, or via 40 Gbps fabrics to DSP engines. For those ISR applications that require the greatest processing power and performance possible, 40 Gbps end-to-end system elements enable the development of large “big iron” scalable HPEC systems that can move terabytes of data. Yet, these high bandwidth board elements also enable designers to address less demanding applications with low- to mid-level subsets of those solutions, saving space, weight, power, and cost.

Alan Baldus Product Marketing Manager, Intel SBCs

Curtiss-Wright Controls Defense Solutions

www.cwcdefense.com