FPGA migration strategies: IP development tools ease Xilinx Virtex-6 to Virtex-7 migration challenges
Migrating to a new FPGA platform is not for the faint of heart, but the challenges can be eased, thanks to modern IP development tools.
When FPGA vendors announce next-generation devices, engineers seek to exploit new features and performance levels. The first step in migrating to a new platform is deciding if the benefits outweigh the effort and possible risks. Key to a Virtex-6 to Virtex-7 migration strategy is the consideration of IP development tools available to ease the process.
Xilinx presents compelling reasons to migrate to their new low-power 28 nm process technology – twice the performance and half the power. This implies that a Virtex-7 silicon device of a given dimension will deliver twice the system-level performance, and a given FPGA function will consume 50 percent less power, compared to a Virtex-6 device.
Many system designers are realizing that even the largest Virtex-6 devices are too small for their application requirements. The prospect of dividing the processing across two FPGAs and the associated power makes the larger Virtex-7 an attractive option. However, this might not be an easy feat; thus, designers must consider the maximum FPGA resources, speeds, and power dissipation for the largest members of the Virtex-6 and Virtex-7 families. Once the decision is made to move forward with migration, IP development tools are integral to simplifying the process.
IP development tools
IP is a general term to describe the logic design that is loaded into the FPGA and ultimately performs the processing task. For more than 10 years, the Xilinx ISE design tools have been the environment of choice for FPGA engineers to create IP. The latest release, ISE Design Suite (version 14), supports FPGA IP development for both Virtex-6 and Virtex-7. Much of the logic and peripheral architecture is similar between the Virtex-6 and -7 silicon families, allowing the majority of IP to be compatible across both platforms. IP typically must chase when new features have been added to the FPGA.
A designer moving or “retargeting” his IP from Virtex-6 to -7 will find the ISE handles much of the migration transparently. Where peripherals have changed, like the PCIe interface now supporting Gen 3, designers will need to integrate new IP to support the new capability. In places where the internal logic structures have been improved such as the new Look Up Table (LUT) architecture, engineers might find hand tuning their IP could be the best way to exploit the new feature and achieve the highest performance. As new FPGA functions are added like integrated analog-to-digital converters, the designer can choose to add a new system level feature to the product by adding new IP to support the converter.
IP development tools moving forward
As FPGA logic densities increase and more functionality is offered in the form of integrated high-speed gigabit serial interfaces and high-performance DSP engines, the FPGA is moving from its role as a processing component in the system to an integrated system-on-chip solution. With this shift comes the requirement for more sophisticated design tools. Xilinx recently announced the Vivado Design Suite to address this exact requirement and provide a path for developers to migrate from the ISE as their application requirements. Vivado offers the FPGA design engineer a tool that handles both programmable logic and programmable system integration.
The core of any FPGA development suite is the synthesis, place, and route tools. A new analytical approach in Vivado enables the designer to balance the design constraints that govern how effectively the tools create deployable FPGA IP. Specifically, parameters like routing congestion, trace length, and overall signal timing can be controlled to produce better results more quickly and reliably. Overall design integration and implementation times can see up to a 4X speed-up over previous approaches. This accelerated development is crucial as FPGA parts become larger and require more development time.
Manage complex FPGA designs
While much of the Virtex-6 IP will port to Virtex-7 using IP development tools, resulting in overall performance increases by nature of the new silicon, the engineer can always choose to further push performance and features by targeting specific attributes of the new architecture. As FPGA devices become larger, designers have the option to use new tools like Vivado to speed development time and manage complex FPGA designs.