Electronic warfare and FPGAs: The need for speed

(EW), the use of the electromagnetic spectrum to foil enemy forces and protect friendly ones, is perhaps the most time-sensitive of all the weapons in the military arsenal: a matter of nanoseconds could make the difference between life and death. That’s why latency is so critical to EW processing systems. If a -guided missile is heading for your aircraft at Mach 5, the aircraft’s radar jammer had better be quick – quick to take in the signal, manipulate it, and retransmit it to fool the adversary with false targets or misleading data on size, distance, heading, speed. Digital RF memories (DRFMs), the specialized RF jammers that do just that, require receive-response latencies of 20 to 100 nanoseconds. Compared to radars – which transmit pulses and receive echoes – DRFMs – which receive pulses and retransmit the signals modulated with jamming techniques – have much more stringent latency requirements.

Survival isn’t getting any easier, as adversaries deploy advanced weaponry on the electronic battlefield. The bandwidth of the signals that are being received by EW systems is expanding, while higher data volumes are coming in on a larger number of channels.

The need for EW speed – never more urgent than now – is driving the incorporation of computationally intensive field-programmable gate arrays (), as well as faster data conversion chips, into front-end EW processing systems.

Fortunately, the commercial off-the-shelf (COTS) parts industry is keeping up in both areas. In recent years, for example, FPGAs have approximately doubled the density of their processing resources while cutting power consumption in half.

The latest devices come in multiple flavors. Some FPGAs feature millions of configurable logic blocks – flexible math operators – giving them massive computational power. Other FPGAs encompass both configurable logic blocks and embedded general-purpose processors (GPPs). In EW applications, the GPP elements of these hybrid chips can be used for monitoring applications or for updating target profiles.

Industry watchers predict that future FPGAs will even incorporate analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), further decreasing end-to-end processing latencies.

Boards shrink

While FPGAs are growing larger and denser, their carrier boards are getting smaller. Multiple FPGAs, along with ADCs, DACs, memory, and associated I/O, can be squeezed into a 3U form factor.

The key to this development is the mezzanine card (FMC) and its newest iteration, FMC+. These industry-standard interface modules enable very-high-speed, direct I/O connections between the / devices lodged on the cards and the host FPGA, reducing end-to-end latency. There are many different FMC/FMC+ implementations, allowing customers the flexibility to meet their needs. What’s more, the modules can easily be changed as higher-performance converters emerge and program needs grow. FMC+ accommodates up to 24 high-speed serial lanes and up to 80 parallel lanes, enabling massively wideband I/O. For EW applications like DRFMs, however, parallel interfaces are preferable to serial interfaces because of latency concerns.

An example of a multifunction, EW-optimized board is ’ VP880, a 3U VPX FMC+ carrier card that features Xilinx’s latest UltraScale FPGA and FPGA-hybrid Zynq UltraScale multiprocessor system-on-a-chip, along with 10 gigabytes of onboard memory. (Figure 1.)

Future challenges

EW technology has evolved over the years to include compute-intensive methods, as well as physical means such as chaff, decoys, and brute-force barrage jamming. The next step may be “cognitive EW,” which uses machine learning algorithms to deploy adaptive and automated jamming techniques. The idea is that if one jamming technique is ineffective against a target radar, the EW system would instantly adjust the parameters to find a solution. This approach would require not only low-latency front-end processing but also powerful GPPs to run the more complex algorithms.

FPGAs, with their wide bandwidth, high throughput, and low latency, will continue to play a key role as EW technology evolves. Heterogeneous architectures, combining FPGAs, hybrid FPGA/GPPs, and even graphics processors, may also be necessary. They could allow the same data to be sifted through multiple processing chains simultaneously or for different purposes, serving the needs of more advanced, next-generation systems. Underlying it all is the flexibility of industry-standard COTS parts that can be combined in novel ways to meet emerging threats.

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Figure 1: The Abaco Systems VP880 3U VPX FMC+ carrier card features Xilinx’s latest UltraScale FPGA and FPGA-hybrid Zynq UltraScale technology.

www.abaco.com