Digital channelizer implemented on COTS FPGA board: A flexible solution for military signal processing
One of the major challenges of modern military Digital Signal Processing (DSP) is dealing with the ever-widening bandwidth of digitized signals. Until fairly recently, analog-to-digital converters (A/D converters) were limited to only hundreds of MHz, so anything beyond that had to be dealt with using traditional RF/analog methodologies. Now that A/D converters are available in the GHz range, much wider band processing is moving to the digital domain.
For military and defense applications such as electronic warfare, electronic surveillance, radar, signals intelligence (SIGINT), and communications, the spectrum of interest can be as much as 20 GHz wide. Even the most advanced digitizers and signal processors can’t directly capture or process that much bandwidth for general purposes. Using the same concepts that have been used for decades, the wideband RF must be broken up into narrower bandwidth “channels” via the analog receiver’s front-end filters and mixers. Although this could be accomplished with a great multiplicity of channels – to the point where the resulting channel bandwidths are directly “digestible” by a digitizer and digital signal processor – this approach drives more complex analog front ends and more digitizers, resulting in increased size, weight, and power, along with additional performance challenges. The general desire is to get to digital as soon as possible, but digitizers have gotten so fast that it is often inconvenient or inefficient to digitally process such wideband channels. This reality has driven the need for a digital channelizer to further narrow the channel to a more optimally digestible width for downstream processing.
As an example, a 20-GHz spectrum might be broken down by the RF receiver into eight channels of 2.5 GHz each, which can then be digitized at 5 Gsamples/sec using readily available A/D converters. This is still a considerable bandwidth for downstream digital processing and feature extraction such as time of arrival and target identification. While digital processing could conceivably be implemented directly on such a wideband signal, there are several reasons to break it down into narrower bandwidth channels before processing, as is shown in Figure 1. Generally speaking, digital processing latency increases with bandwidth due to the need for larger filters and FFTs, so narrower bands reduce latencies. A narrower bandwidth will also capture less noise and irrelevant signals, so narrowband processing will result in higher signal-to-noise ratio results than wideband processing of the same signal of interest. In addition, processing power (GMACs) is proportional to bandwidth; in many applications where a large signal bandwidth is under consideration, only a portion of that bandwidth need be analyzed at any given time. The channelizer allows the system to dynamically choose what portion(s) of spectrum to process, which reduces the necessary processing rate and power consumption compared to the full spectrum being processed all the time.
The system benefits of using a digital channelizer to further divide the incoming bandwidth before processing may now be clear, but how to implement one is not. Implementation requires creation of complex modulators operating on the incoming data stream, typically using filter banks created from DFTs, FFTs, and/or modulated cosine techniques, all of which involve detailed algorithmic and architectural tradeoffs. Although the underlying techniques are well understood, the implementation and optimization is quite complicated in practice.
FPGAs handle digitizing, channelizing
FPGAs are particularly well-suited for the task with their ability to directly interface to high-speed digitizers, in addition to their inherent processing parallelisms, hardened DSP blocks, and significant power advantages. At the same time, however, it is well understood that implementing complex algorithms, such as a channelizer, in an FPGA is challenging and difficult to both maintain and modify. Hardware design-flow challenges in this instance include writing behaviorally correct Hardware Description Language (HDL) algorithms; integrating components for I/O, control, and memory; minimizing resource utilization; optimizing latencies; and ultimately achieving timing closure. All of those challenges are revisited with each design iteration, modification, and specification change.
Well aware of these challenges, Altera has developed a complete channelizer IP block implementation for their DSP Builder tool. DSP Builder allows for high-performance push-button HDL generation of DSP algorithms directly from MathWorks’ Simulink environment, providing a graphic block-level flow that delivers tremendous ease-of-use while automatically handling hardware design-flow problems. For example, the synthesis tool uses fused datapath techniques to reduce resources and latencies, automates timing closure, optimizes for device family and speed grade, and takes advantage of special hardware features such as DSP blocks. Algorithmic changes are performed in a Simulink-like environment in which users can take advantage of parameterization to experiment with relevant features, such as number of channels, to achieve the required system and hardware performance. In addition to this powerful and time-saving channelizer block, standard and advanced blocksets are also provided that can greatly simplify the implementation of processing the channelizer output for feature extraction and signal identification.
System-level FPGA project integration is also facilitated with Altera’s Qsys system-integration tool, which saves significant time and effort during the FPGA design process by automatically generating interconnect logic to connect functions and subsystems, including DSP Builder algorithms. An integrated Qsys project implementing the channelizer is shown in Figure 2. Note that a complete 64-channel channelizer project, including the essential A/D converter interface, internal memory, and interconnects, takes only a small percentage of the FPGA’s resources (depending, of course, on the specific implementation and FPGA size), leaving the vast majority of the FPGA’s resources available for additional application processing such as feature extraction and signal identification.
With a channelizer core now available, along with an integrated FPGA example project, actual hardware is needed to deploy this integrated channelizer project in the real world, rather than just in a development and simulation environment. The COTS S56X 6U VPX board from BittWare provides two independent Statix V FPGAs, each with identical memory, communications, host interfaces, and VITA 57/FMC sites for modular I/O; this board can therefore support two separate instances of the channelizer project. The VITA 57/FMC sites can be populated with any number of A/D converters from Bittware or third parties to adapt the I/O for specific application requirements.
For the purposes of demonstrating the channelizer implementation and providing a reference platform, an FMC with a 10-bit A/D converter that runs at 5 Gsamples/sec was chosen and populated on both sites: the 3F126-FMC from BittWare as shown in Figure 3. The resulting board assembly can then be populated in a 6U VPX chassis, such as BittWare’s VRDP-CH, with access to debug and communications via backplane, rear-breakout, and/or a separate breakout board. BittWare provides the A/D converter interface block that is integrated into the Qsys project; their standard software and support toolkit, BittWorks II Toolkit, provides the means to load, reset, and debug the FPGA and will monitor the board voltages, currents, and temperatures. The board’s ARM processor, which runs Linux, is an on-board host/controller that can be used to implement command, control, and backend processing.
This reference platform provides a COTS solution for getting a wideband signal digitized and delivered to a well-supported FPGA which, when loaded with the example project, implements a complete wideband channelizer. Each FPGA parametrically ”channelizes” 2.5 GHz of wideband input out of the box, resulting in each COTS board handling 5 GHz, with the bulk of the FPGA and ARM resources still available to the user. An ultra-wideband 20-GHz input can be easily accommodated by placing four of these S56X platforms in a 6U VPX chassis, providing a solution that is flexible, expandable, and scalable, all in a modest size, weight, and power envelope.