COTS processing drives modern electronic warfare systems
Designers of signal-processing systems for electronic warfare (EW) applications faced with requirements for reduced size, weight, and power (SWaP) along with more processing power are creating multifunction systems that leverage high-speed field-programmable gate array (FPGA) technology.
Electronic warfare, for decades, has been a kingdom rife with customized systems and stovepipe technology based on closed architectures. As enemy threats become more sophisticated, EW designers face pressure to create systems that can adapt and respond effectively in real time. Their efforts are resulting in multifunction systems that marry different types of EW, such as signals intelligence (SIGINT) and electronic intelligence (ELINT), as well as EW and radar functions in one box.
“I see a trend toward more multifunction systems to handle both radar and EW processing in a single system,” says Lorne Graves, Technical Director at Mercury Systems in Chelmsford, Massachusetts. “Some will be CPU-centric and some will be FPGA-centric in terms of processing; it will just depend on the mission. It just makes sense to combine the functions of a radar and EW system in the same box, as they have common processing components, while only differing when it comes to RF components.
“Multifunction systems also enable development of high-level hardware that can allow one to run digital algorithms for a combination of CPU and FPGA resources,” Graves continues. “You could have the ability to switch between jamming, radar tracking, and communication elements.”
“ELINT, SIGINT, and radar systems all have similar hardware, such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), FPGAs, maybe graphics processing units (GPUs) or central processing units (CPUs) as well as similar arrays or sets,” says Noah Donaldson, Vice President of Product Development for Annapolis Micro Systems in Annapolis, Maryland. “Therefore, designers industrywide are looking to meld all that functionality into one system that, for example, can look at signals while at the same time performing jamming functions.”
“In years past, a SIGINT asset would go and gather information for a mission, and the signals basically had the ability to understand the electromagnetic spectrum and we used that as strategic advantage,” Graves says. “Now when you look at it from an anti-access/area denial (A2/AD) perspective, you can have the SIGINT payload fly in with EW capability that can protect and spoof. This requires sophisticated processing elements such as high-performance CPUs and FPGAs that reduce overall platform SWaP.”
Radar vs. EW processing
“Radar systems transmit a pulse out that then it comes back, so they need more sensitivity since they are trying to receive a reflected signal,” Graves says. “These systems need more dynamic range and more processing gain. Also, how much processing you need is often defined by the waveform you use to transmit and receive.
“EW systems need to handle much more instantaneous bandwidth and ingest more data at wider bandwidth and they require low latency, which is crucial for responding to threats in near real-time,” he continues. “EW systems typically do not require the same sensitivity as radars, but they cover a much broader bandwidth.”
Latency continues to be a challenge, as EW processing systems evolve from parallel to serial architectures. “Data converter manufactures are increasingly moving from parallel to serial interfaces, such as JESD204B. Unfortunately, when you move from parallel to serial interfaces, latencies increase,” says Denis Smetana, Senior Product Manager for FPGA products at Curtiss-Wright. “The growing demand for more bandwidth is fueling the move toward serial lines in order to reduce the challenges of having very wide, fast data buses which are difficult to route on PCBs. What’s more, parallel interfaces consume a lot of pins on digital converter devices and FPGAs. There’s concern in the industry that with JESD204B, latency is much higher than has been previously experienced with parallel low-voltage differential signaling (LVDS) interfaces, making it unsuitable for low-latency EW functions. The good news is that there is a new version in the works, JESD204C, as well as other options, that provide promising approaches to resolving the serial latency issue.”
FPGAs, mainly those from Xilinx and Altera (now Intel’s Programmable Logic Group), are providing performance advantages for military EW and enabling a concept called cognitive EW.
“Cognitive EW represents a significant new step in EW, moving beyond the ability to just make decisions on the fly to being able to create new responses on the fly,” Smetana says. “Adaptive responses are predetermined and then used at given times depending on the environment and mission. Cognitive EW will help deal with threats never encountered before, by creating the appropriate response for that scenario in real time. To accomplish this, cognitive EW techniques also require learning capability.
“To enable true cognitive EW, not only do you need more processing, you also need to move the processing closer to the sensors to enable real-time analysis,” Smetana continues. “In addition, cognitive EW, like adaptive EW, requires the ability to reconfigure existing hardware, for example with FPGAs, to ensure the system is optimized for SWaP.”
“FPGA-centric types of EW systems in particular are enabling a concept called cognitive EW,” Mercury’s Graves says. “There is a big push toward cognitive EW as we need real-time adaptation in environments where we encounter threats never seen before. These adversarial threats are able to adapt very quickly because the adversaries have access to similar commercial technology leveraged in modern radar systems. FPGA-based solutions enable the number-crunching and statistical analysis necessary for countering these new threats as FPGAs provide wider bandwidth and lower latency.”
EW FPGA advantages
The addition of cognitive EW into radar systems is coinciding with the blurring of capability between traditional processors and FPGAs.
“As the lines start to blur between pure FPGAs and pure processors, a move towards the convergence of processor and FPGA functions in EW and radar signal-processing systems has emerged,” Smetana explains. “At the same time, the RF environment is becoming more complex. That makes it imperative for both radar and EW functions to work with each other more effectively. The radar system needs to know what EW techniques are being used, and the EW system needs to make use of radar information. Historically, FPGAs tend to be used for front-end signal processing where multiple parallel sensor data streams need to be handled. Processors are used to handle the interpretation of the data and the calculation of appropriate responses. As the EW battlefield becomes more complex and intertwined, the use of embedded processor cores in FPGAs and the use of FPGA logic within microprocessors will become more prevalent.”
Unlike CPUs and GPUs, FPGAs offer “many unique features critical for military and aerospace systems,” says Rodger Hosking, Vice President and founder of Pentek in Upper Saddle River, New Jersey. “Their reconfigurability lets designers arrange and interconnect hardware resources in parallel to match even the toughest real-time requirements. We are now delivering FPGA products with 3,600 DSP engines and two million logic cells, with the ability to reconfigure those elements under software control during a mission to adapt to evolving threats. FPGAs also provide configurable interfaces for wideband sensors like ADCs and DACs operating at gigahertz sampling rates, as well as gigabit serial system interfaces like PCIe, Serial RapidIO, and Infiniband. Sophisticated memory controllers for the fastest SDRAMs support read/write data rates up to 1.6 GHz. With these diverse, high-performance capabilities, FPGAs deliver complete acquisition, processing, and interfacing subsystems ideally suited for EW and radar systems that require fast I/O, low latency, and computational intensity.” (Figure 1.)
Easing FPGA development
Experts at Annapolis Micro Systems have enhanced their CoreFire Next Design Suite development product with a new tool called Open Project Builder. “It enables users to have more flexibility when developing code for FPGAs by allowing them to choose to develop code in CoreFire with or without VHDL,” Donaldson says. “Developing in CoreFire without VHDL is faster, but many users still choose to work in VHDL due to processes they already have in place. With Open Project Builder, they now can develop in VHDL too and then port it to other hardware. Open Project Builder also enables the use of FPGA IP from other sources such as High Level Synthesis (HLS) and comes with a board support package for all Annapolis Wildstar boards. The CoreFire tool is included with the Annapolis hardware. There is no longer a separate price for it.”
Open Project Builder is a dataflow-based development system that enables FPGA programming. It supplies user-made connections between programming modules, or cores, and manages multiple domain requirements automatically. The development suite does not require hardware design languages as the user creates dataflow diagrams by dragging and dropping cores, or building blocks, from the libraries and connecting their ports.
Many older EW systems are custom solutions based on closed architectures that did not lend themselves to smooth tech refreshes. These systems – once quite capable of meeting traditional EW threats – now face an adversary that can adapt quickly. These new capacities call for systems based on industry standards and open architectures to enable quick capability upgrades. Two examples of this type of a retrofit leveraging VITA standards were performed by Mercury Systems and 4DSP (Austin, Texas).
VME SIGINT upgrade
“A big challenge for EW processing suppliers such as Mercury is to provide this advanced EW processing on older platforms,” Graves says. “We did that recently by deploying a new, open architecture, VME-based product – the 6U DCM-2RT-VXS Transceiver – to go into an older SIGINT system as part of a retrofit for a quick reaction capability on naval platforms that are encountering adversarial threats not seen before. The upgrade gives that system the ability to adapt and change to the threats. By utilizing advanced scheduling algorithms, the multifunctional capabilities I mentioned earlier could be achieved. (Figure 2.)
“The system we upgraded was not an open system, so we went in and replaced the custom solution with an open system interface that could work with the older RF requirements. It had the capability to handle these threats from an RF perspective, but it needed a boost in processing power.
“By retrofitting these older custom solutions with open architectures, you can reduce the total life cycle cost of the systems,” Graves continues. “The openness enables future tech refreshes that do not have huge cost or integration burdens. There is an OpenRFM equivalent in development where we’ve taken what we’ve done in VME and scaled that over to VPX. It is still early in the development cycle, but I can say it will rely on FPGA functionality via Xilinx Virtex 7 FPGAs. We are using Xilinx, as our customer’s existing algorithm was developed in an older Xilinx family.”
VPX and the airborne EW pod
“Engineers at 4DSP were tasked with designing a processing solution for an EW platform that had to fit in an airborne pod that would provide attack protection and support,” says Richard Ary, Vice President of Sales at 4DSP. “The requirements called for intense signal-processing capability in a small form factor. We came up with a solution, VPX167, that had enhanced computing power with an RF front end, a down-converter, and a digital mechanism for transporting data to an FPGA then converting it back out again and applying the appropriate algorithm.”
4DSP then took the algorithm to the lab system, shrunk it, and placed it on the pod, Ary continues. “The 3U single-board computer (SBC) in the lab was the same 3U SBC for the pod. Using FMC, which by its nature is a small form factor, made it easy to go from a lab environment to a deployable system. The secret sauce is the modular backplane, FlexVPX. We essentially break the backplane in half to connect it with the cable in a 3U VPX form factor. It was the only way to fit the solution into the pod. The other key component in the solution is the multigigahertz wideband transceiver, made by PMI, which is mounted on a VPX module that fits in 3U VPX slot.
“FlexVPX, originally developed at the U.S. Naval Research Laboratory under the sponsorship of the Navy’s Office of Naval Research, enabled an elongated form factor in a condensed space,” Ary says. “The integrated LRU also created a significant weight savings, replacing four boxes with one to drop the weight from 160 to 40 pounds which helped maintain the weight requirements for aircraft.
“We took advantage of various VITA standards to minimize development time while maintaining the same level of performance. This started out as a custom design that leveraged open architectures and COTS standards so that it can be easily upgraded for tech refreshes down the road. The solution is conduction-cooled and is FPGA-agnostic. While this was designed for one particular FPGA family, there is nothing stopping the end user from using another brand if they wish,” adds Ary.
OpenVPX across the globe
OpenVPX for EW applications is not only a trend in the U.S., as companies in Europe and Africa are also leveraging the standard for EW signal processing.
ApisSys engineers in Archamps, France, have designed the modular AF209, which is based on the VITA 57 FPGA Mezzanine Card standard for EW applications. It comes with a single-channel 12-bit DAC that is capable of as much as 4.5 Gsps. The AF209 DAC channel is AC-coupled with an output bandwidth wider than seven GHz for a signal of -3 dBm (450 mVpp). It is also fully supported on ApisSys 3U VPX FPGA processing engines. (Figure 3.)
In South Africa, experts at Parsec are offering the VF36x family of FPGA-based 3U OpenVPX modules that leverage Altera’s FPGA Stratix V family and Texas Instruments KeyStone DSP in a single system. Its VITA57.1 FMC provides custom I/O and a PCI Express switch for scaling multiple boards. The Parsec product can be air- or conduction-cooled.