Common EW and radar systems for emerging military missions

2Due to shrinking Department of Defense (DoD) budgets and ever-decreasing platform size, the need to use common apertures and sensor chain elements for Electronic Warfare (EW) and radar systems is becoming a necessity. System developers must use common elements from Radio Frequency (RF) to processing to build such systems. The linchpin of these types of sensor-based systems is the I/O interface between the RF and processing elements. FPGAs have traditionally been used as this I/O interface, but now they are serving as an integral part of the processing subsystem on common EW radar systems.

As sequestration begins to affect multiple programs and budgets continue to shrink, the DoD must look for ways to maximize the financial value across various programs. Not only is cost a major factor on today’s platforms, but the need to reduce payload Size, Weight, and Power (SWaP) on small Unmanned Aerial Vehicles (UAVs) is also a necessity. As UAV operations move into areas with contested airspace, not only will radar and Intelligence, Surveillance, and Reconnaissance (ISR) systems be needed, but electronic warfare systems will become an essential part of virtually every mission.

To optimize performance across these platforms, electronic systems providers must rely on a Modular Open Systems Architecture (MOSA) as well as on commercially available products. Commercially available products help reduce the cost of systems by reducing Non-Recurring Engineering (NRE) expense and can free up developers to focus on system integration and algorithm development. This focus can result in an electronic system delivered in less time with optimal results and a lower overall system cost. Typically, radar and EW system design have been two separate disciplines that used similar components to produce electronic systems for vastly different requirements. The common element used in both these types of systems is the Field Programmable Gate Array (FPGA)-based I/O interface. Today’s FPGA, as it has matured with Digital Signal Processing (DSP) power exceeding typical General-Purpose Processors (GPPs) and with integrated Advanced RISC Machines (ARM)-based cores that provide low-power-control logic, is now considered a vital asset in most EW and radar systems.

Common radar and EW systems

To understand how FPGA processing plays a major role in fused radar and EW systems, it is important to first review a typical airborne radar system and then a typical EW system. Review of these two systems allows for identification of areas of overlap within the hardware components of each system. A typical airborne radar system has an antenna aperture with a high-power transmit and receive switch. Four receivers and one exciter provide the RF-to-Intermediate Frequency (IF) conversion in the system. The conversion from IF to digital data is performed on the FPGA processing element. Well-suited for beam-forming and pulse compression, the FPGA board will typically perform some elements of the radar processing; the FPGA processing element will provide the preprocessed data to the DSP elements, which then provide the detection, tracking, and target-recognition algorithms. The final element, a control processor, is responsible for network interfaces, control, status, and low-level control of the entire system.

EW systems tend to be broadband in nature, while radar systems are relatively narrowband. An EW system also contains an antenna aperture and has a wideband RF receiver and exciter, which provide RF-to-IF conversion. The conversion from analog to digital data is once again provided by the FPGA processing element, which also performs various operations to prevent enemy radar from tracking the platform. Countermeasures may include barrage jamming, spot jamming, and Digital Radio Frequency Memory (DRFM). FPGAs, due to their flexibility and adaptability, are able to easily handle the DRFM and other countermeasures. The DSP element in EW systems is typically responsible for determining what type of technique to use against enemy radar – therefore it is often referred to as a threat manager or scheduler. The DSP element and control processor are similar and may be one and the same in EW systems.

Typical radar and EW systems use common elements throughout. While the system bandwidths may vary greatly, the EW systems overlap those of the radar systems. For example, if a radar system is working within X-band (8-12 GHz), the typical EW system covers VHF through Ku band. Therefore, the antenna, RF receivers, and exciters for the EW system could be adapted for use in the radar systems. There are numerous tradeoffs (outside the scope of this article) that need to be made to develop common antenna and RF elements, however, such as the fact that the IF/analog conversion rates are very similar but the instantaneous bandwidths of the signals vary widely. Today’s latest data-converter products offer sufficient resolution (dynamic range) and frequency coverage to be utilized in both systems. The I/O interface from the data conversion to the processing domain has already been dominated by the FPGA for years. The processing elements developed by commercial companies have become commonplace in both radar and EW systems. In fact, the use of open standards and operating systems like Linux has made COTS processing boards easily adaptable for both types of systems.

FPGA processing to unite radar and EW systems

FPGAs, once used as “glue logic” in most designs to “glue” interfaces together, have become processing workhorses in many of today’s radar and EW systems. The maturation of FPGAs to include thousands of dedicated multipliers, highly optimized memory interfaces, and high-speed serial transceivers has turned them into one of an algorithm developer’s favorite tools. With the integration of embedded low-power ARM processors into these devices, a new level of system fusion is becoming a reality.

The processing flow

Typical radar systems use the FPGA for digital beam-forming and pulse compression. Detection and tracking algorithms are then performed in processing elements such as Intel- or Freescale-based GPP boards. With dual ARM cores available in FPGAs, there are multiple multi-GHz processing elements available to perform the detection and tracking algorithms. To enable the EW system, designers must take advantage of the same powerful building blocks within the latest generation of FPGAs. The EW processing flow – see Figure 1 – relies on the immense parallel-processing capabilities of the FPGAs. For example, in a DRFM countermeasure, the system designers may create multiple false targets or create a Doppler shift on the radar return to “spoof” the enemy radar system. The EW system developer may also use the large amount of embedded memory in the FPGA to develop waveforms used in barrage or spot jamming. The final aspect of the EW system that may be performed in the FPGA is the threat manager. Again, the embedded processor is used as the control element in the system to develop the highly complex state logic needed to make the system a reality.

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Figure 1: Common EW and radar processing flow.
(Click graphic to zoom by 1.9x)

The ability to embed all of this functionality into FPGAs, while difficult, is now becoming a reality. COTS boards with multiple FPGAs can be partitioned to “fuse” the systems together. For example, latency-critical EW functions can be performed at the leading edge of the data conversion, followed by radar-processing elements. A high-level block diagram of a common FPGA-based processing system is shown in Figure 1. Mercury Systems offers products spanning from RF to processing; these products focus on delivering the full sensor chain to system developers.

EW and radar system fusion is becoming a necessity

With shrinking budgets and smaller platforms, EW and radar systems must begin to use common components to reduce Size, Weight, Power, and Cost (SWaP-C). U.S. DoD missions need to operate for longer durations and function in highly contested airspace. Leveraging COTS technology for FPGA processing elements and taking full advantage of the technological leaps in FPGA computing power, the fusion of EW and radar systems is rapidly becoming a necessity. As warfighters and the platforms they use are asked to do more with less, this fusion will give service members the capabilities to protect themselves and execute missions across the globe.

A. Lorne Graves is the lead architect for IF, Digital, and Integrated RF/IF products at Mercury Systems. With more than 20 years of experience designing mixed-signal circuitry and FPGAs as well as expertise in mixed-signal and RF technology, he has served as the business development lead on several key radar, SIGINT, and electronic warfare programs, working directly with various defense prime contractors. He was a key contributor of the architecture for the award-winning SCFE (VME and Critical Systems magazine) product. Before joining Mercury in 2003, he was a senior engineer for a major networking company, and prior to that, he served as a Field Applications Engineer (FAE) for two electronic component manufacturers. Mr. Graves earned his bachelor’s degree in electrical engineering from the University of Alabama, Huntsville. He can be reached at agraves@mrcy.com.

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