Building highly parallel rugged computers for electronic warfare
Electronic warfare (EW) systems are among the most challenging embedded systems to design and deploy. Not only do they require voracious amounts of signal processing, they also require more mundane server-style processing (for signal library maintenance, data logging, etc.) and are often packaged in extremely size, weight, and power (SWaP)-constrained environments such as under wing pods. As a result, advanced EW systems can benefit from consolidating workloads on a single machine with the means to efficiently execute these two very different processing problems using parallel virtual machine (VM) execution. Modern commercial off-the-shelf (COTS) 3U VPX boards based on Intel server-class processors are a compelling option for these sorts of systems.
Each generation of EW systems increases the demands for high-performance processing and increasingly larger bandwidth for both streaming data in and out of the system as well as for interprocessor communications. Military systems designers face an ever-growing need to meet escalating requirements and provide platforms that can be packaged and deployed in harsh environments. Furthermore, proprietary systems no longer make sense from an engineering resource, budget, and deployment schedule perspective. Facing the limitations of tightening budgets, defense OEMs must find a way to cost-effectively meet the mounting data throughput and processing needs of these systems. A key way the market has curbed costs is to move from closed, proprietary solutions to open-standard COTS solutions in smaller form factors that are durable and reliable.
Matching technology needs
Suppliers of both components and boards/systems have responded in meeting higher performing standardized solution needs. Leveraging the consumer electronics drive for larger numbers of cores, streaming video and audio processing, and greater integration, Intel and other processor suppliers are offering components with these features that include the added bonus of extended temperature ratings and longer-than-typical consumer life cycles that can satisfy lengthier embedded defense application lifespans. Boards and system suppliers are making use of these components and developing both board-level and packaged systems solutions that simultaneously push performance limits and I/O features while maintaining tough SWaP limits and driving down costs. This approach is a real win for the EW market, which generally will use every ounce of performance they can fit into a package.
This insertion of commercially available technologies into defense-ready platforms continues a trend that was started in the early to mid-1990s. Over that time, defense system integrators have become very adept at utilizing high performance embedded computing (HPEC)-like technologies such as multicore and multicomputing platforms linked with high-speed buses or data links to solve their particular problems. As a result, current systems designers can expect to leverage tens (or even hundreds) of processor cores, each linked by very-high-speed/low-latency data paths using commercially available – and often standards-based – operating systems (OSs), software libraries, and middleware. This way gives the designer unprecedented power to integrate and deploy the system with a minimum of effort and time. It also means that designers generally no longer need to compromise on either performance or I/O bandwidth, and don’t need to move to proprietary or customized solutions.
Driving electronic warfare innovation
High-density HPEC platforms that, for example, integrate the server-class Intel Xeon processor D-1540, provide the basis for continued EW innovation. These types of sophisticated processing systems enable military system developers to take advantage of the extensive capital and operational efficiencies provided by isolated workloads configured to dynamically share common resources specifically enabling multipurpose or multifunction EW systems. For instance, developers can use such systems to powerfully consolidate workloads into a single system to run both jamming and surveillance EW applications.
Jammers often operate by taking a radar signal in and transmitting a corresponding different signal to effectively mask a vehicle’s true position, velocity, or even composition. To do this, jammers require extremely fast digital signal processing (DSP) capabilities such as those offered by the AVX2 floating-point vector math units in the Intel Xeon processor D. By bringing exceptional eight-core performance and advanced features into dense, lower-power industry-standard systems-on-chip (SoCs), EW developers can scale their designs for quick data capture and processing. Additional features supporting fast distributed data transfer are reliable PCI Express (PCIe) Gen3 and 10 Gigabit Ethernet (GbE) that deliver extremely low latency at as fast as 10 GHz per lane.
Jamming applications can also benefit from using the interprocessor switch fabric these new dense HPEC platforms offer between payload slots. Based on PCIe and 10 GbE, they give designers a plug-and-play solution capable of moving data at ultra-high speeds by implementing extremely fast serial link point-to-point connections between boards. Using advanced standards-based communications fabrics enables developers to quickly implement or port applications using standard TCP/IP or other communications protocol stacks, resulting in high performance and efficient system convergence. In addition, many devices and subsystems offer native PCIe, which allows immediate use of an existing infrastructure, thereby lowering latency, cost, and power.
Different EW systems can have different demands on a system. Electronic surveillance, for its part, requires much more detailed and compute-intensive processing of sensor data. The Xeon processor D not only delivers essential DSP performance, but it offers extremely efficient general-purpose processing as well as a rich assortment of peripheral I/O such as SATA III. In addition, the Xeon processor D offers virtualization technology (Intel VT), which enables the system developer to direct these divergent tasks to efficiently share the processing hardware. This functionality makes it an ideal platform for electronic surveillance applications.
Next-generation VPX-based boards, based upon the OpenVPX standard, leverage the power of the Xeon-D processor in a flexible 3U package. These boards combine the DSP and general-purpose processing features of the Xeon processor D with advanced ECC DDR4 memory and an embedded graphics controller. The result is a rugged and flexible computing platform ideal for EW applications. For math-intensive surveillance operations, these octo-core-based boards fully use the AVX2 SIMD units, where each core has two AVX2 units and can provide up to 128 floating point operations per clock, or a potential 230.4 gigaflops of DSP performance. Able to be employed in the wide range of complex and extreme electronic surveillance environments, these platforms support widening the operational margins on the backplane to support intelligent multifunction EW solutions.
The OpenVPX standard – inherently known for its high performance, rugged operation in harsh environments, and small form factor – enable today’s HPEC solutions to be used to simplify logistics, installation, and maintenance of complex EW systems. These platforms can be air- and conduction-cooled, offering extended operating temperature capability where airflow temperature is controlled on each slot; moreover, payload boards can be held in standby mode to meet low-energy surveillance requirements.
Advanced HPEC platforms also take the guesswork out of mastering multigigabit rate communication on standard backplane technology by supporting PCIe and 10 GbE, between all boards in the backplane, across the full operational domain of a rugged computer design. This broadened bandwidth capacity enables systems integrators to evolve applications to more effectively respond to immediate threats. The combination of dense processing with rich standards-based communications fabric and I/O connectivity means that these platforms are equally suited for streaming signal- or image-processing EW applications that include combined jammer and electronic surveillance functions.
In addition, new multicore high performance platforms increasingly help meet tight budgets and future-proof their technology investments. For example, the virtualization features integrated in new HPEC systems enable OEMs to leverage a single application design based on mainstream technologies to be easily adapted to match CPU count, available I/O, form factor, memory, or other hardware evolution needs.
More efficient EW design
A key evolution in HPEC design is the balancing of CPU power with I/O bandwidth to increase overall performance. Traditional HPECs have featured excellent CPU power based on continually increasing computing performance, but I/O bandwidth has not always kept up with processor performance, causing potential bottlenecks and performance issues.
A balanced HPEC approach is the Kontron StarVX: It enables ease of development because it is based on only nonproprietary technology such as x86, Linux, TCP/IP, and PCIe, which eliminates niche-based deployments and reduces obsolescence risk. It delivers the I/O bandwidth and IP sockets EW application designers need in order to successfully use mainstream IT servers and deploy the system unmodified.
Additionally, Kontron’s VxFabric API technology provides a TCP/IP protocol over the PCIe infrastructure towards the application to help accelerate the design process. Its 10 GbE switch and a PCIe switch can be complemented with two single star data planes for 10 GbE and for PCIe, respectively. Designers are able to use this API with TCP/IP sockets that enable multicore computing node architectures that permit high-speed socket-based communication between blades using multiple switched-fabric interconnects within the backplane.
Leveraging data center performance benefits
Bringing data center performance benefits to EW applications, the Xeon processor D delivers 10 times greater performance than currently available in other ruggedized HPEC platforms. Using the eight-core version of the processor D, computing blades are able to support heavier throughput by delivering as much as 3.4 times faster performance per node and up to 1.7 times the better performance per watt when compared to the Intel Atom processor C2750.
Intel’s latest processors include support for error-correcting code memory, combined with enhanced hardware-based Intel VT and Intel Advanced Encryption (AES-NI). This advanced integration is inherently SWaP-C optimized, and offers long-life availability and enhanced silicon reliability through Intel’s 10-year simulation aging tests, making it an optimal engine for HPEC platforms.