A quiet revolution against RTL - Xilinx DSP kits develop into more than reference designs

FPGAs have gotten so large and complex that even veteran silicon designers tremble at the prospect of figuring out efficient routing to utilize all the Look Up Tables (LUTs), logic elements, routing interconnects, DSP slices, and gigabit transceivers. This is despite having the best tools money can buy from Cadence, Synopsys, or Mentor. And with Xilinx’s recent announcement of stacked-chip interconnects leading up to an unheard-of 2 million gate Virtex-7 FPGA in 2011, things are gonna get tougher. Only hard-core FPGA designers will use the damn things, and they’ll be the guys who absolutely need million-point FFTs, wacky OFDM algorithms in LTE cellular base stations, or AESA radar processors.

It doesn’t have to be this way. It’ll only be a tough design flow if you stick with the traditional semiconductor design route using HDL and RTL. But other options exist, including model-based design a la MathWorks, and coding in high-level languages such as C/C++. These are not so popular today, though they’re certainly viable, and Xilinx is about to give non-RTL alternatives a swift kick to the front of the line. I believe the company’s new DSP Targeted Design Platform development kits are going to be the catalysts to usher in a move to non-HDL FPGA designs (www.xilinx.com/technology/dsp.htm). After all, who the heck wants to be an IC designer when what they really want is to design systems?

For a couple of years, Xilinx has partnered with companies like Avnet to make available hardware reference boards called Targeted Design Platforms for things like image tracking and signal processing. They’re doing it again, with three new ones just announced in December:

  • Virtex-6 FPGA Design Kit with Integrated AD/DA
  • Spartan-6 FPGA DSP Kit
  • Spartan-6 FPGA/OMAP Co-processing Kit

Each is a stand-alone board complete with demos, drivers, appropriate software, I/O modules (where applicable), extensive documentation, and even royalty-free reference design docs (gerbers and schematics) so customers can replicate the design – or modify it for their own system. I could go on and on about the coolness of each of these boards and cite their technical specs, but that’s not what is revolutionary about these kits. In fact, they’re really quite evolutionary by looking at the specs. Two of them use FMC for I/O – one with an impressive card by partner 4DSP boasting a 250 MSps A/D into a DDC, routed back through the Virtex-6 logic to an 800 MSps DUC into a D/A. This particular kit is intended for gangbuster performance in systems needing up to 1,000 GMACs, implemented by seasoned FPGA designers doing “bare metal” RTL coding with optimized and probably existing legacy DSP algorithms.

“So what,” you say, “it’s evolutionary” … except for the fact that Xilinx also includes the ability to code this board in C/C++ using software from vendors AutoESL or Synopsys. And they’ve also included interfaces to a SysGen flow that bolts onto MathWorks’ Simulink model-based environment. Using Xilinx- and BDTi-generated benchmarks with mildly optimized code, the performance of this particular Virtex-6 kit is almost as good with the high-level tools as it is with RTL, and the logic utilization is also nearly as good. And to boot, changes to the FPGA design can be done in modular code blocks (in C/C++ or Simulink) and realized within hours as opposed to days when done in RTL. Simplicity and time savings are huge advantages that will save designers and their employers some real coin.

But there’s more. The Virtex-6 kit is meant for FPGA designers already doing DSP. The other two kits are geared for either a non-FPGA DSP designer thinking about moving to FPGAs (the Spartan-6 DSP kit) or for processor designers (using an ARM-based TI OMAP L-138) out of horsepower who must add an FPGA to meet performance requirements. In both of these cases, Xilinx demonstrates how easy and painless it is to add an FPGA to achieve 3x, 10x, and even more performance with a mere $10 Spartan-6 device. And since these two kits are optimized for C/C++ and Simulink flows, the barrier to entry for RTL-averse system designers is practically nil. Way cool, and revolutionary.

Xilinx’s quiet introduction of the kits is preparing the world to stick FPGAs in all designs that need more performance or headroom with minimal cost. In effect, they’re set to dramatically expand their market to non-FPGA users by making it easy to choose and program an FPGA. With high-level language or model-based tools, who needs to worry about RTL? Let the IC designers fret about that. The rest of us just want to design systems. Now that’s a revolution in the making.

Chris A. Ciufo, Editor cciufo@opensystemsmedia.com